module data_select(
	input			clk					,	
	input			rst_n				,	
										
	input			rx_done				,
	input	[7:0]	oder_data			,
	input			auto_user_en		,	//外部用户控制采样率的使能
	input			frequency_user_en	,   //外部用户控制串口发送频率数据的使能
	input			frequency_tx_done	,   //频率数据发送结束的信号
										
	output	reg		send_singal_en		,   //发送波形数据的串口的使能
	output	reg		send_frequency_en	,   //发送频率数据的串口的使能
	output	reg		delay_sample_en			//控制delay_sample的采样率的使能

);
parameter 	oder_frequency		= 8'h46,//F			//频率检测状态
			oder_delay_smaple	= 8'h41;//A			//数据处理状态
			
parameter cnt_tx_done_max	=	3;

localparam
	send_sigal		=	2'd0,
	send_frequency	=	2'd1,
	delay_sample	=	2'd2;

reg [4:0] cnt_tx_done;
reg [4:0] cnt_time;
// always@(posedge clk or negedge rst_n)	
	// if(!rst_n)
		// cnt_tx_done <= 10'd0;
	// else if(cnt_tx_done == cnt_tx_done_max - 1'b1)
		// cnt_tx_done <= 10'd0;
	// else
		// cnt_tx_done <= cnt_tx_done + 1'b1;
	
reg [1:0] state;
always@(posedge clk or negedge rst_n)
	if(!rst_n) begin
		send_singal_en		<= 1'b0;
	    send_frequency_en	<= 1'b0;
	    delay_sample_en		<= 1'b0;
		cnt_tx_done <= 5'd0;
		cnt_time <= 5'd0;
		state				<= send_sigal;
	end
	else begin 
		case(state)
			send_sigal		: begin
				if(rx_done == 1'b1) begin
					if(oder_data == oder_frequency) begin
						send_singal_en		<= 1'b0;
						send_frequency_en	<= 1'b1;
						delay_sample_en		<= 1'b0;
						cnt_tx_done <= 5'd0;
						state	<= send_frequency;
					end
					else if(oder_data == oder_delay_smaple) begin
						send_singal_en		<= 1'b0;
						send_frequency_en	<= 1'b0;
						delay_sample_en		<= 1'b1;
						cnt_time			<= 5'd0;
						state	<= delay_sample;
					end
				end
				else begin
					send_singal_en		<= 1'b1;
					send_frequency_en	<= 1'b0;
					delay_sample_en		<= 1'b0;
					state	<= state;
				end
			end
			
            send_frequency	: begin
				send_singal_en		<= 1'b0;
				delay_sample_en		<= 1'b0;
				if(frequency_tx_done == 1'b1) begin
					cnt_tx_done <= cnt_tx_done + 1'b1;
					if(cnt_tx_done >= cnt_tx_done_max) begin
						cnt_tx_done <= 5'd0;
						state	<= send_sigal;
						send_frequency_en	<= 1'b0;
					end
				end
				else
					state	<= state;
			end
            delay_sample	: begin
				send_singal_en		<= 1'b0;
				send_frequency_en	<= 1'b0;
				cnt_time <= cnt_time + 1'b1;
				if(cnt_time >= 15) begin
					cnt_time <= 5'd0;
					delay_sample_en	<= 1'b0;
					state			<= send_sigal;
				end

			end

			default: state <= send_sigal;
		endcase
	end




endmodule